The present invention relates to a switching system for exchanging time-shared multiplex communication data such as voice and data using a fixed-length cell with a routing header, or more in particular to a switching system suitable for exchanging the burst exchange data and the channel exchange data such as voice integrally.
A versatile and economical switching system is required which is capable of integrally handling communications not only of the bit rate (64 Kb/s) of typical telephone voice but also of various bit rates from low-speed (several hundred b/s) data to video signal (several Mb/s) and various characteristics (burst and real time characteristics).
A promising method expected to meet this requirement involves switching all data uniformly using a fixed-length cell with a header containing routing data. The switching system disclosed in a report entitled "A study of an Integrated Line/Packet Message Channel", presented to Exchange Division 1832, National General Conference (1988) in memory of the 70th anniversary of the foundation of the Electronic Information Communications Society is an example. In this example, all communications data is transferred by use of a fixed-length block called a "cell". The switching is derived from a space switch, and in order to prevent a plurality of cells having the same address from colliding with each other in the space switch, a timed switching function is provided for each incoming highway. Further, the timed switching function includes a switching memory and a waiting buffer memory to realize a line exchange mode requiring a real time characteristic such as telephone voice and a burst exchange mode in which data is sent in burst fashion with some delay which may be allowed. The line exchange mode cell is handled preferentially not through a buffer memory for guaranteeing the real time characteristic, while the burst exchange mode cell is kept waiting in the buffer memory and is processed when there is any empty time slot.
Another example of the prior art is "TDM Switching System" disclosed in the JP-A-59-135994. This system, though lacking an express description of the concept of handling two types of characteristics including the line exchange mode and the burst exchange mode, is equipped with a function to replace the fixed-length cell in terms of time by use of a buffer memory. In the process, the same buffer memory is used for waiting for a cell and switching thereof. In other words, in order to accomplish the required waiting, the write address into the cell buffer memory is known from the header. The system comprises waiting matrix means to be stored according to the address of the cell.
In the case where a plurality of fixed-length cells are used for the switching operation, the fact that the cell addresses are not always uniformly distributed may cause the cells destined for the same address to be concentrated temporarily into an overcrowded condition or the cells to be lost by memory overflow. In the system disclosed in the report of the present applicant cited first above, a waiting buffer memory is provided for each highway outgoing to each address to avoid such an overcrowded condition. This buffer memory is required to have a sufficient capacity to store as many cells as required to prevent overflow, and that it is necessary that such a buffer memory is required for each address separately. The resulting problem of this configuration is the necessity of a great capacity of memory. The second-cited switching system (JP-A-59-135994), on the other hand, comprises a single buffer memory for all incoming highways and a plurality of waiting matrix means for the cell addresses respectively to store only the addresses of the buffer memory. This construction is capable of absorbing the lack of uniformity among the cells with a comparatively small storage capacity. The periodic use of the write addresses of the buffer memory, however, places the system with the buffer memory in logically the same state as if fixedly divided for each address. When the waiting time for a given cell of the waiting matrix exceeds a predetermined length, for example, the same write address is used to cause an overwrite of the buffer memory in spite of the fact that there still remain cells yet to be read. The cell overwritten is erased undesirably.